NFEN=0, RXDESEL=0, ABCS=0, ABCSE=0, BRME=0, ACS0=0, BGDM=0, PADIS=0
Serial Extended Mode Register
| ACS0 | Asynchronous Mode Clock Source Select 0 (0): External clock input 1 (1): Logical AND of compare matches output from the internal GPT. These bit for the other SCI channels than SCIn (n = 1, 2) are reserved. |
| PADIS | Preamble function Disable 0 (0): Preamble output function is enabled 1 (1): Preamble output function is disabled These bits for the other SCI channels than SCIn (n = 0, 3 to 9) are reserved. |
| BRME | Bit Rate Modulation Enable 0 (0): Disable bit rate modulation function 1 (1): Enable bit rate modulation function |
| ABCSE | Asynchronous Mode Extended Base Clock Select 1 0 (0): Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register 1 (1): Baud rate is 6 base clock cycles for 1-bit period These bits for the other SCI channels than SCIn (n = 0, 3 to 9) are reserved. |
| ABCS | Asynchronous Mode Base Clock Select 0 (0): Select 16 base clock cycles for 1-bit period 1 (1): Select 8 base clock cycles for 1-bit period |
| NFEN | Digital Noise Filter Function Enable 0 (0): In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple I2C mode: Disable noise cancellation function for SCLn and SDAn input signals 1 (1): In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple I2C mode: Enable noise cancellation function for SCLn and SDAn input signals |
| BGDM | Baud Rate Generator Double-Speed Mode Select 0 (0): Output clock from baud rate generator with normal frequency 1 (1): Output clock from baud rate generator with doubled frequency |
| RXDESEL | Asynchronous Start Bit Edge Detection Select 0 (0): Detect low level on RXDn pin as start bit 1 (1): Detect falling edge of RXDn pin as start bit |